# ISRO CS 2015

 Question 1
Which of the given number has its IEEE-754 32 bit floating point representation as 0 10000000 110 0000 0000 0000 0000 0000
 A 2.5 B 3 C 3.5 D 4.5
Digital Logic & Number representation    Number Representation    ISRO CS 2015
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Question 1 Explanation:
IEEE-754 32 bit floating point representation has excess-128 notation and first MSB represents sign bit for mantissa, next 8 bits represents the exponent(excess 127) and last 23 bits represent the value of mantissa. Given, floating point = 0 10000000 110 0000 0000 0000 0000 0000 0 at MSB represents that mantissa is positive. Next 8 bits, i.e. 10000000 = exponent = 2128 but as it is excess 127 notation, so actual value of exponent = 2128 - 127 = 21 Value of mantissa in normalized form = 1.110 0000 0000 0000 0000 0000 Answer = (1.11)2 * 2 = 3.5 Option (C) is correct.
 Question 2
The range of integers that can be represented by an n bit 2’s complement number system is:
 A - 2n - 1 to 2n - 1 - 1 B - (2n - 1 - 1) to (2n - 1 - 1) C - 2n - 1 to 2n - 1 D - (2n - 1 + 1) to (2n - 1 - 1)
Digital Logic & Number representation    Number Representation    ISRO CS 2015
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Question 2 Explanation:
In 2's complement numbers, the range of integers are from -2n-1 to 2n-1 - 1 Option (A) is correct.
 Question 3
How many 32K X 1 RAM chips are needed to provide a memory capacity of 256K-bytes?
 A 8 B 32 C 64 D 128
Computer Organization and Architecture    ISRO CS 2015    CPU control design and Interfaces
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Question 3 Explanation:
Number of chips required = (256 K x 8) / (32 K x 1) = 64 Option (C) is correct.
 Question 4
A modulus -12 ring counter requires a minimum of
 A 10 flip-flops B 12 flip-flops C 8 flip-flops D 6 flip-flops
Digital Logic & Number representation    ISRO CS 2015    Sequential circuits
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Question 4 Explanation:
A ring counter requires 'n' flipflops for 'n' number of states. A modulus-12 counter has 12 states starting from 0000 to 1011, atleast 12 bits are required to design a modulus-12 counter.
 Question 5
The complement of the Boolean expression AB ( B'C + AC ) is
 A ( A' + B' ) + ( B + C' )( A' + C' ) B ( A' + B' ) + ( BC' + A'C' ) C ( A' + B' )( B + C') + ( A + C' ) D ( A + B )( B' + C )( A + C )
Digital Logic & Number representation    ISRO CS 2015    Logic functions and Minimization
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Question 5 Explanation:
Applying DeMorgan's law and after complementing: ( AB ( B'C + AC ))' = (A + B)' + (B'C + AC)' = (A' + B') + ( B'C)' (AC)' = (A' + B') + ( B + C')(A' + C') Option (A) is correct.
 Question 6
The code which uses 7 bits to represent a character is
 A ASCII B BCD C EBCDIC D Gray
Number Representation    ISRO CS 2015
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Question 6 Explanation:
Basic ASCII encodes 128 specified characters and thus use 7 bits to represent each of these characters whereas Extended ASCII needs 8-bit for each character representation as it has a total set of 256 characters. Extended Binary Coded Decimal Interchange Code (EBCDIC) is an 8-bit binary code for numeric and alphanumeric characters. BCD encoding uses 4 bits to represent each digit from the range 0 to 9 in its binary form. In case of Gray codes, any number of bits can be used to represent a character, according to the requirement. So, Option (A) is correct.
 Question 7
If half adders and full adders are implemented using gates, then for the addition of two 17 bit numbers (using minimum gates) the number of half adders and full adders required will be
 A 0, 17 B 16, 1 C 1, 16 D 8, 8
Digital Logic & Number representation    ISRO CS 2015    Combinational Circuits
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Question 7 Explanation:
A Half Adder is used to add 2 single-bit binary numbers and a Full Adder is used to add 3 one-bit binary numbers which include two sum bits and one carry bit. To add two 17 bit numbers using minimum gates, the least significant bits of both the numbers can be added using a half adder and for remaining 16 bits of both the numbers, full adders can be used. 1 Half Adder and 16 Full Adders will be required. So, option (C) is correct.
 Question 8
Minimum number of multiplexers required to realize the following function,f = A'B'C + A'B'C' Assume that inputs are available only in true form and Boolean constant 1 and 0 are available.
 A 1 B 2 C 3 D 7
Digital Logic & Number representation    ISRO CS 2015    Combinational Circuits
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Question 8 Explanation:
The function can be simplified:
f = A'B'(C+C') = A'B'
Since, we have to take the inputs in their true form(i.e, there is no way to get A' or B' directly), TWO Multiplexers will be required.
• 1st MUX will be used to get the function: AB
• 2nd MUX will be used to complement the output from the first, i.e, get A'B'
NOTE:There are other ways to solve this too.
Mux1: I0 = 0 I1 = A S = B Output = 0 + AB = AB
Mux2: I0 = 1 I1 = 0 S = AB (output from Mux1) Output = (AB)' = A'B' (which is the desired output)
 Question 9
The number of 1's in the binary representation of (3*4096 + 15*256 + 5*16 + 3) are:
 A 8 B 9 C 10 D 12
Digital Logic & Number representation    Number Representation    ISRO CS 2015
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Question 9 Explanation:
```Given expression = 3*4096 + 15*256 + 5*16 + 3
= (2 + 1)*4096 + (8 + 4 + 2 + 1)*256 + (4 + 1)*16 + 2 + 1
= (2 + 1)*212 + (23 + 22 + 2 + 1 )*28 + (22 + 1)*24 + 2 + 1
= (213 + 212) + (211 + 210 + 29 + 28) + (26 + 24) + 2 + 1
As 213 is 1 followed by 12 zeros, 212 is 1 followed by 11 zeros and so on,
adding all these numbers give total 10 one's```
So, option (C) is correct.
 Question 10
The boolean expression AB + AB'+ A'C + AC is independent of the boolean variable
 A A B B C C D None of these
Digital Logic & Number representation    ISRO CS 2015    Logic functions and Minimization
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Question 10 Explanation:
```AB + AB' + A'C + AC
= A(B + B') + C(A + A')
= A + C(/pre)
As the expression is independent of 'B', option (B) is correct.
```
There are 80 questions to complete.
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