Time required to execute and fetch an entire instruction is called instruction cycle. It consists:
- Fetch cycle – The next instruction is fetched by the address stored in program counter (PC) and then stored in the instruction register.
- Decode instruction – Decoder interprets the encoded instruction from instruction register.
- Reading effective address – The address given in instruction is read from main memory and required data is fetched. The effective address depends on direct addressing mode or indirect addressing mode.
- Execution cycle – consists memory read (MR), memory write (MW), input output read (IOR) and input output write (IOW)
The time required by the microprocessor to complete an operation of accessing memory or input/output devices is called machine cycle. One time period of frequency of microprocessor is called t-state. A t-state is measured from the falling edge of one clock pulse to the falling edge of the next clock pulse.
Fetch cycle takes four t-states and execution cycle takes three t-states.
Timing diagram for fetch cycle or opcode fetch:
Above diagram represents:
- 05 – lower bit of address where opcode is stored. Multiplexed address and data bus AD0-AD7 are used.
- 20 – higher bit of address where opcode is stored. Multiplexed address and data bus AD8-AD15 are used.
- ALE – Provides signal for multiplexed address and data bus. If signal is high or 1, multiplexed address and data bus will be used as address bus. To fetch lower bit of address, signal is 1 so that multiplexed bus can act as address bus. If signal is low or 0, multiplexed bus will be used as data bus. When lower bit of address is fetched then it will act as data bus as the signal is low.
- RD (low active) – If signal is high or 1, no data is read by microprocessor. If signal is low or 0, data is read by microprocessor.
- WR (low active) – If signal is high or 1, no data is written by microprocessor. If signal is low or 0, data is written by microprocessor.
- IO/M (low active) and S1, S0 – If signal is high or 1, operation is performing on input output. If signal is low or 0, operation is performing on memory.
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