GATE | GATE MOCK 2017 | Question 42

Consider a 3-stage pipeline with stage delay of 80, 70 and 90 ns respectively. Assume constant clock rate. What is the time taken to process 100 instructions if registers are used as buffer between stages with a delay of 10 ns ?

(A) 10,200 ns

(B) 10,000 ns

(C) 10,050 ns

(D) 11,000 ns

Answer: (A)

Highest time period of a stage is selected for the clock cycle to avoid overlapping.
Hence,90 ns + 10ns for buffers =100ns will be a clock cycle time period.

Now , time taken for 1st instruction – 100 * 3 (time period for 3 stages)
Time taken for 2-100 instructions – 99 * 100 (pipeline is used so rest of the instructions only take one stage)

So, total time for 100 instruction = 300 ns + 9900 ns = 10,200 ns

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