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GATE | GATE MOCK 2017 | Question 42
Consider a 3-stage pipeline with stage delay of 80, 70 and 90 ns respectively. Assume constant clock rate. What is the time taken to process 100 instructions if registers are used as buffer between stages with a delay of 10 ns ?
(A)
10,200 ns
(B)
10,000 ns
(C)
10,050 ns
(D)
11,000 ns
Answer
Please comment below if you find anything wrong in the above post
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