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GATE | Gate IT 2008 | Question 38
A non pipelined single cycle processor operating at 100 MHz is converted into a synchronous pipelined processor with five stages requiring 2.5 nsec, 1.5 nsec, 2 nsec, 1.5 nsec and 2.5 nsec, respectively. The delay of the latches is 0.5 nsec. The speedup of the pipeline processor for a large number of instructions is
(A)
4.5
(B)
4.0
(C)
3.33
(D)
3.0
Answer
Please comment below if you find anything wrong in the above post
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