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GATE | Gate IT 2008 | Question 38

  • Last Updated : 19 Nov, 2018

A non pipelined single cycle processor operating at 100 MHz is converted into a synchro­nous pipelined processor with five stages requiring 2.5 nsec, 1.5 nsec, 2 nsec, 1.5 nsec and 2.5 nsec, respectively. The delay of the latches is 0.5 nsec. The speedup of the pipeline processor for a large number of instructions is
(A) 4.5
(B) 4.0
(C) 3.33
(D) 3.0

Answer: (C)

Explanation: For non pipelined system time required = 2.5+1.5+2.0+1.5+2.5 =10

for pipelined system = Max(stage delay)+Max(Latch delay)

=> 2.5+0.5 = 3.0

speedup = time in non-pipelined system/time in pipelined system

= 10/3 = 3.33

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