GATE | GATE IT 2006 | Question 78

A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. The sequence of instructions corresponding to the statement X = (S – R * (P + Q))/T is given below. The values of variables P, Q, R, S and T are available in the registers R0, R1, R2, R3 and R4 respectively, before the execution of the instruction sequence.

2006_78

The number of Read-After-Write (RAW) dependencies, Write-After-Read( WAR) dependencies, and Write-After-Write (WAW) dependencies in the sequence of instructions are, respectively,
(A) 2, 2, 4
(B) 3,2,3
(C) 4,2,2
(D) 3,3,2


Answer: (C)

Explanation: Read After Write:
1. ADD ->MUL (R5)
2. MUL -> SUB (R6)
3. SUB-> DIV (R5)
4. DIV->STORE (R6)
Write After Read
1. MUL -> SUB (R5)
2. DIV -> STORE (R6)
Write After Write
1. ADD -> SUB (R5)
2. MUL – DIV (R6)


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