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GATE | Gate IT 2005 | Question 45

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A hardwired CPU uses 10 control signals S1 to S10, in various time steps T1 to T5, to implement 4 instructions I1 to I4 as shown below:

table

Which of the following pairs of expressions represent the circuit for generating control signals S5 and S10 respectively?

((Ij+Ik)Tn indicates that the control signal should be generated in time step Tn if the instruction being executed is Ij or lk)

 
(A)
S5=T1+I2â‹…T3 and

S10=(I1+I3)â‹…T4+(I2+I4)â‹…T5
(B) S5=T1+(I2+I4)â‹…T3 and

S10=(I1+I3)â‹…T4+(I2+I4)â‹…T5
(C) S5=T1+(I2+I4)â‹…T3 and

S10=(I2+I3+I4)â‹…T2+(I1+I3)â‹…T4+(I2+I4)â‹…T5
(D) S5=T1+(I2+I4)â‹…T3 and

S10=(I2+I3)â‹…T2+I4â‹…T3+(I1+I3)â‹…T4+(I2+I4)â‹…T5


Answer: (D)

Explanation:

Quiz of this Question


Last Updated : 19 Nov, 2018
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