Skip to content
Related Articles

Related Articles

GATE | GATE CS 2021 | Set 2 | Question 63
  • Last Updated : 08 Mar, 2021

Consider a pipelined processor with 5 stages, Instruction Fetch(IF), Instruction Decode(ID), Execute (EX), Memory Access (MEM), and Write Back (WB). Each stage of the pipeline, except the EX stage, takes one cycle. Assume that the ID stage merely decodes the instruction and the register read is performed in the EX stage. The EX stage takes one cycle for ADD instruction and the register read is performed in the EX stage, The EX stage takes one cycle for ADD instruction and two cycles for MUL instruction. Ignore pipeline register latencies.

Consider the following sequence of 8 instructions:

ADD, MUL, ADD, MUL, ADD, MUL, ADD, MUL 

Assume that every MUL instruction is data-dependent on the ADD instruction just before it and every ADD instruction (except the first ADD) is data-dependent on the MUL instruction just before it. The speedup defined as follows.

Speedup = (Execution time without operand forwarding) / (Execution time with operand forwarding)

The Speedup achieved in executing the given instruction sequence on the pipelined processor (rounded to 2 decimal places) is _____________ .
(A) 1.875


Answer: (A)

Explanation:

Quiz of this Question
Please comment below if you find anything wrong in the above post

My Personal Notes arrow_drop_up
Recommended Articles
Page :