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GATE | GATE CS 2019 | Question 12
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A15 to A0. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?
(A)
C800 to CFFF
(B)
CA00 to CAFF
(C)
C800 to C8FF
(D)
DA00 to DFFF
Answer
Please comment below if you find anything wrong in the above post
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