# GATE | GATE CS 2018 | Question 45

• Last Updated : 16 Aug, 2021

The size of the physical address space of a processor is 2P bytes. The word length is 2W bytes. The capacity of cache memory is 2N bytes. The size of each cache block is 2M words. For a K-way set-associative cache memory, the length (in number of bits) of the tag field is

(A) P − N − log2K
(B) P − N + log2K
(C) P − N − M − W − log2K
(D) P − N − M − W + log2K

Explanation: Physical Address Space = 2P Bytes. Word Length is 2W bytes, which means each word is of size 2W bytes.
Cache memory size = 2N Bytes and Tag Size = 2X Bytes.
Physical address is P – W bits
Number of blocks in cache = 2(N-W-M)

It is a K-way set associative cache memory, each set in cache will have K-blocks.
So, Number of sets = 2(N-W-M)/ K
SET bits will be N-W-M-logk
Offset bits will be M

We know,
TAG bits = Main memory bits – SET bits – offset bits
So, TAG bits(x) = P – W – (N-M-W-logk)- M
= P – W – N + M + W + logk – M
x = P – N + logk

Option (B) is Correct.

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