# GATE | GATE-CS-2017 (Set 1) | Question 24

• Last Updated : 16 Aug, 2021

Consider a two-level cache hierarchy L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache 0.1, the L2 cache experience on average. 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ______________.

Note: This questions appeared as Numerical Answer Type.
(A) 0.05
(B) 0.06
(C) 0.07
(D) 0.08

Explanation: Let 1000 instructions generated

Therefore,
Miss rate of L2 cache = (memory references generated by L2 cache) / (memory references generated by L1 cache)
= 7 / 140 = 0.05

Alternate Solution

On Average, 1.4 memory accesses are required for one instruction execution.
So, for 1000 instructions, 1400 accesses are needed.
Number of misses occurred in cache L2 for 1000 instruction = 7/1400 = 0.005
Miss rate of L2 cache = misses occured in L2 cache / miss rate in L1 cache
= 0.005 / 0.1 = 0.05 (A)

This solution is contributed by Sumouli Chaudhary.

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