GATE | GATE-CS-2015 (Set 1) | Question 65

Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is __________.
(A) 3.2
(B) 3.0
(C) 2.2
(D) 2.0


Answer: (A)

Explanation:

Speedup = ExecutionTimeOld / ExecutionTimeNew

ExecutionTimeOld = CPIOld * CycleTimeOld
                  [Here CPI is Cycles Per Instruction]
                 = CPIOld * CycleTimeOld
                 = 4 * 1/2.5 Nanoseconds
                 = 1.6 ns

Since there are no stalls, CPInew can be assumed 1 on average.
ExecutionTimeNew = CPInew * CycleTimenew
                 = 1 * 1/2
                 = 0.5

Speedup = 1.6 / 0.5 = 3.2

Refer http://www.cs.berkeley.edu/~pattrsn/252F96/Lecture2a.pdf for more information on this topic.

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