GATE | GATE CS 2013 | Question 65
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I1, I2, I3, …, I12 is executed in this pipelined processor. Instruction I4 is the only branch instruction and its branch target is I9. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is
Pipeline will have to be stalled till Ei stage of l4 completes, as Ei stage will tell whether to take branch or not. After that l4(WO) and l9(Fi) can go in parallel and later the following instructions. So, till l4(Ei) completes : 7 cycles * (10 + 1 ) ns = 77ns From l4(WO) or l9(Fi) to l12(WO) : 8 cycles * (10 + 1)ns = 88ns Total = 77 + 88 = 165 ns
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