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GATE | GATE CS 2012 | Question 54

  • Last Updated : 19 Nov, 2018

A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit.
The number of bits in the tag field of an address is

(A) 11
(B) 14
(C) 16
(D) 27


Answer: (C)

Explanation: A set-associative scheme is a hybrid between a fully associative cache, and direct mapped cache. It’s considered a reasonable compromise between the complex hardware needed for fully associative caches (which requires parallel searches of all slots), and the simplistic direct-mapped scheme, which may cause collisions of addresses to the same slot (similar to collisions in a hash table). (source: http://www.cs.umd.edu/class/spring2003/cmsc311/Notes/Memory/set.html). Also see http://csillustrated.berkeley.edu/PDFs/handouts/cache-3-associativity-handout.pdf

 

Number of blocks = Cache-Size/Block-Size = 256 KB / 32 Bytes = 213

Number of Sets = 213 / 4 = 211



Tag + Set offset + Byte offset = 32
Tag + 11 + 5 = 32
Tag = 16


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