GATE | GATE CS 2011 | Question 65

Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.

GATECS2011Q50

If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?
(A) 000
(B) 001
(C) 010
(D) 011


Answer: (D)

Explanation: P’ = R
Q’ = (P + R)’
R’ = QR’ Given that (P, Q, R) = (0, 1, 0), next state P’, Q’, R’ = 0, 1, 1

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D flip flop truth table



D Q(t+1)
0 0
1 1

Initially (p,q,r) =(0,1,0)
D for p=R
D for q=NOT(p xor r)
D for r= (not)r.q
So Q(t+1) for(p,q,r)
p=>r=0 so p=0
q=> NOT(p xor r) => 1      so q=1
r=>(not)r.q => 1         so r=1
(p, q, r) = (0, 1, 1)

Alternative approach –
Truth table of a D Flip-Flop-
 \begin{tabular}{|c|c|} \hline D_{t} & Q_{t+1}\\ \hline 0 & 0\\ \hline 1 & 1\\ \hline \end{tabular}
By looking at the circuit diagram, it is clear that the boolean expressions of P, Q, and R are-
Here the subscript t refers to the current clock cycle, and the subscript (t+1) refers to the next clock cycle.
Q_{P(t+1)} = P_{t+1} = R_t
Q_{Q(t+1)} = Q_{t+1} = R_{t}' P_{t}'
Q_{R(t+1)} = R_{t+1} = Q_{t} R_{t}'

 \begin{tabular}{|c|c|c|} \hline D_{t} & Q_{t+1}\\ \hline 0 & 0\\ \hline 1 & 1\\ \hline \end{tabular}
This explanation is provided by Chirag Manwani.

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