GATE | GATE CS 2011 | Question 28

On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.

```
Initialize the count to 500
LOOP: Load a byte from device
Decrement the count
If count != 0 go to LOOP ```

Assume that each statement in this program is equivalent to machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute.

The designer of the system also has an alternate approach of using DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.
What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?
(A) 3.4
(B) 4.4
(C) 5.1
(D) 6.7

Explanation:

``` Explanation:
STATEMENT                                           CLOCK CYCLE(S) NEEDED
Initialize the count to 500                                            1
LOOP: Load a byte from device                                                2
Decrement the count                                                    1
If count != 0 go to LOOP                                               1

Interrrupt driven transfer time = 1+1+500×(2+2+1+1+1) = 3502
DMA based transfer time = 20+500*2 = 1020
Speedup = 3502/1020 ≈ 3.4

Source: http://clweb.csa.iisc.ernet.in/rahulsharma/gate2011key.html```
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