A main memory unit with a capacity of 4 megabytes is built using 1M × 1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is
(A) 100 nanoseconds
(B) 100×210 nanoseconds
(C) 100×220 nanoseconds
(D) 3200×220 nanoseconds
Explanation: Number of chips required for 4MB MM = (4 * 2^20 * 8) / (1 * 2^20) = 32 chips
In a refresh cycle, a whole row of a memory chip is refreshed at once. This implies the given time of 100 ns for one refresh operation refreshes one row of memory chip. Since there are 1K=2^10 such rows, time for refreshing a whole chip would be: 2^10 * 100 ns.
Second question arises, how to arrange these chips as there can be many possible arrangements. There is a logical arrangement provided in the problem statement itself as “1M x 1 bit chip”. This indicates that to make a “1M x 32 bits” MM, we need to arrange all 32 chips in a line. It is to be noted that a row in all chips in series can be refreshed in one refresh cycle. This makes the total time to refresh the 4MBytes of memory as same as that of one chip. Hence, time required to refresh MM = 100 * 2^10 ns.
So, option (B) is correct.
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