GATE | GATE CS 2008 | Question 77

Delayed branching can help in the handling of control hazards
The following code is to run on a pipelined
processor with one branch delay slot:

I1: ADD R2R7+R8
I2 : SUB R4 R5-R6
I3 : ADD R1 R2+R3
I4 : STORE Memory [R4][R1]
BRANCH to Label if R1== 0

Which of the instructions I1, I2, I3 or I4 can legitimately occupy the delay slot
without any other program modification?
(A) I1
(B) I2
(C) I3
(D) I4


Answer: (D)

Explanation: It can’t be l1 or l3, because directly or indirectly they are taking part in the branching decision.
Now we can have both l2 and l4 after the branching decision statement and  the order of I2 and I4 matters because in I2 we are getting the final value in register R4 and in instruction we are saving contents of R1 in memory whose address is stored in the register.

So If we made I2 to be the instruction after branch then the value in the first loop itself the value stored in memory location whose address is stored in R4 would be wrong because it actually should have been updated first by R5-R6.So  I4 is correct.



So (D) is correct option.

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