GATE | GATE CS 2008 | Question 36

Which of the following are NOT true in a pipelined processor?

I.  Bypassing can handle all RAW hazards.
II. Register renaming can eliminate all register 
    carried WAR hazards.
III. Control hazard penalties can be eliminated by 
     dynamic branch prediction.

(A) I and II only
(B) I and III only
(C) II and III only
(D) I, II and III


Answer: (B)

Explanation: I – False, Bypassing can’t handle all RAW hazard, consider when any instruction depends on the result of LOAD instruction, now LOAD updates register value at Memory Access Stage (MA), so data will not be available directly on Execute stage.

II – True, register renaming can eliminate all WAR Hazard.



III- False, It cannot completely eliminate, though it can reduce Control Hazard Penalties

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