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GATE | GATE-CS-2007 | Question 37
  • Last Updated : 19 Nov, 2018

Consider a pipelined processor with the following four stages:

IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Back

The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage dependson the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?

ADD R2, R1, R0       R2 <- R0 + R1
MUL R4, R3, R2       R4 <- R3 * R2
SUB R6, R5, R4       R6 <- R5 - R4  

(A) 7
(B) 8
(C) 10
(D) 14


Answer: (B)

Explanation: Explanation:

Order of instruction cycle phases

IF”  ID”  EX”  WB”



We  have 3 instructions. which represents wait in pipeline due to result dependently.

12345678
R2!R1!R0IFIDEXWB
R4!R3!R2IFIDEXEXEXWB
R6!R5!R4IFID--EXWB

 

This is the table shows the cycle phases and number of cycles require for given instruction.

No. of cycles required=8

So (B) is correct option.

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