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GATE | GATE-CS-2006 | Question 81

  • Difficulty Level : Hard
  • Last Updated : 19 Nov, 2018

A CPU has a 32 KB direct mapped cache with 128-byte block size. Suppose A is a twodimensional array of size 512×512 with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.

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for (i=0; i<512; i++) {
   for (j=0; j<512; j++) {
      x += A[i][j];


for (i=0; i<512; i++) {
   for (j=0; j<512; j++) {
      x += A[j][i];

P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2 .

The value of the ratio M1/M2 is:
(A) 0
(B) 1/16
(C) 1/8
(D) 16

Answer: (B)

Explanation: [P2] runs the loops in a way that access elements of A in row major order and [P2] accesses elements in column major order.
No of cache blocks = CacheSize/BlockSize = 32KB / 128 Byte = 256
No. of array elements in Each Block = BlockSize/ElementSize = 128 Byte / 8 Byte = 16

Total Misses for [P1] = ArraySize * (No. of array elements in Each Block) / (No of cache blocks) = 512 * 512 * 16 / 256 = 16384

Total Misses for [P2] = Total Number of elements in array (For every element, there would be a miss) = 512 * 512 = 262144.

Ration m1/m2 = 16384 / 262144 = 1/16.

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