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GATE | GATE-CS-2006 | Question 8

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  • Difficulty Level : Hard
  • Last Updated : 15 Jun, 2021
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You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of f by 180°?
(A) A
(B) B
(C) C
(D) D

Answer: (C)

Explanation: We assume the D flip-flop to be negative edge triggered. 

In option (A), during the negative edge of the clock, first flip-flop inverts complement of ‘f’(we get f as the output).
But, the complement of the output of first flip-flop(i.e. f’) is given as the input to the second flip-flop.

The second flip flop is enabled by ‘clk’.
The output at the second flip flop is f’+90 degrees (as +ve edged clk at output delays it by 90 degrees). Thus f is delayed by 270 degrees.
So, A is not the correct option. 

Following the above procedures as in (A) we will get:In option (B) and (D), the output is ‘f’.
But, we want inverted ‘f’ as the output. So, (B) and (D) can’t be the answer. In option (C), the first flip-flop is activated by ‘clk’.
So, the output of first flip-flop has the same phase as ‘f’. But, the second flip-flop is enabled by complement of ‘clk’.

Since the clock ‘clk’ has a duty cycle of 50% , we get the output having phase delay of 180 degrees. 
Therefore, (C) is the correct answer. 

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