Consider two cache organizations: The first one is 32 KB 2-way set associative with 32-byte block size. The second one is of the same size but direct mapped. The size of an address is 32 bits in both cases. A 2-to-1 multiplexer has a latency of 0.6 ns while a kbit comparator has a latency of k/10 ns. The hit latency of the set associative
organization is h1 while that of the direct mapped one is h2.
The value of h1 is:
(A) 2.4 ns
(B) 2.3 ns
(C) 1.8 ns
(D) 1.7 ns
Explanation: Cache size = 32 KB = 32 * 210 bytes
Cache block size = 32 bytes
Number of blocks = 2
Total combinations are :
= cache size / (Number of blocks * block size)
= 32 * 210 / (2 * 32)
Therefore, number of index bits = 9
Since, cache block size is 32 bytes i.e. 25 bytes.
Number of offset bits = 5
So, number of tag bits = 32 – 9 – 5 = 18
Hit latency (h1) = 0.6 + (18 / 10) ns = 2.4 ns
Thus, option (A) is correct.
Please comment below if you find anything wrong in the above post.
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