GATE | GATE-CS-2005 | Question 79

Consider the following data path of a CPU.

GATECS2005Q78

The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation – the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR

The instruction “add R0, R1” has the register transfer interpretation R0 < = R0 + R1. The minimum number of clock cycles needed for execution cycle of this instruction is.

(A) 2
(B) 3
(C) 4
(D) 5


Answer: (B)

Explanation: Minimum number of clock cycles (execution only) = 3
1) load Y
2) input R1, add
3) return result to GPRs R0

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