GATE | GATE-CS-2005 | Question 79
Consider the following data path of a CPU.
The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation – the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR
The instruction “add R0, R1” has the register transfer interpretation R0 < = R0 + R1. The minimum number of clock cycles needed for execution cycle of this instruction is.
It is clear from the diagram that the operands must be loaded in S & T registers before the ALU can perform any operation. To move the operands from R0 & R1 to S & T two clock cycles are needed. It is also given that the ALU & the registers are of identical size, so the operations can be performed in a single stage requiring only one clock cycle (if the size of the operands is bigger than the ALU, then the operands are split and the operations are performed in stages).
1) S <= R0 : Move operand from R0 to S register.
2) T <= R1 : Move operand from R1 to S register.
3) R0 <= S+T : Add the operands and store back in R0.
Therefore for execution phase 3 clock cycles are needed.
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