GATE | GATE-CS-2005 | Question 68

A 5 stage pipelined CPU has the following sequence of stages:

IF — Instruction fetch from instruction memory,
RD — Instruction decode and register read,
EX — Execute: ALU operation for data and address computation,
MA — Data memory access - for write access, the register read
     at RD stage is used,
WB — Register write back.
Consider the following sequence of instructions:
I1 : L R0, 1oc1;        R0 <= M[1oc1]
I2 : A R0, R0;           R0 <= R0 + R0
I3 : S R2, R0;           R2 <= R2 - R0
Let each stage take one clock cycle.

What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of I1 ?
(A) 8
(B) 10
(C) 12
(D) 15


Answer: (A)

Explanation:
If we use operand forwarding from memory stage :

	T1	T2	T3	T4	T5	T6	T7	T8
l1	IF	RD	EX	MA	WB
l2		IF	RD		EX	MA	WB
l3			IF		RD	EX	MA	WB

If we don’t use operand forwarding :

	T1	T2	T3	T4	T5	T6	T7	T8	T9	T10	T11
l1	IF	RD	EX	MA	WB
l2		IF			RD	EX	MA	WB
l3					IF			RD	EX	MA	WB

Thus, clock cycles = 8 / 11
Since, 11 is not in the option. So, clock cycles = 8.


Thus, option (A) is correct.


Please comment below if you find anything wrong in the above post.

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