A 4-bit carry lookahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic.
(A) 4 time units
(B) 6 time units
(C) 10 time units
(D) 12 time units
Explanation: Let the input carry to the first adder be denoted by C1.
Now, to calculate C2 we need = P1C1 + G1 = 4 gate levels (P1 takes 2 gate levels)
to calculate S1 we need = P1 XOR C1 = 2 + 2 = 4 gate levels.
Since it is a Carry look ahead adder, computing C3 , S2 doesn’t have to wait for carry output C2 from the previous adder as C2, C3 etc will get computed at the same time.
S2 is computed as = P2 XOR C2 = P2.C2′ + P2′.C2
= P2 (P1.C1 + G1 )’ + P2′ (P1.C1 + G1) [ notice that we are not using the output carry from first adder C2 anywhere here ]
which can be implemented using 4 gate levels.
also C3 can be computed by using 4 gate levels and so on…
so the overall propagation delay is 4 gate level as the outputs at Si , Ci are available at the respective full adders after 4 gate levels = 4 time units.
To understand it with more clarity draw the carry look ahead adder circuit and then check it.
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