A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns.
Suppose a process has only the following pages in its virtual address space: two contiguous code pages starting at virtual address 0x00000000, two contiguous data pages starting at virtual address 0×00400000, and a stack page starting at virtual address 0×FFFFF000. The amount of memory required for storing the page tables of this process is:
(A) 8 KB
(B) 12 KB
(C) 16 KB
(D) 20 KB
Breakup of given addresses into bit form:- 32bits are broken up as 10bits (L2) | 10bits (L1) | 12bits (offset) first code page: 0x00000000 = 0000 0000 00 | 00 0000 0000 | 0000 0000 0000 so next code page will start from 0x00001000 = 0000 0000 00 | 00 0000 0001 | 0000 0000 0000 first data page: 0x00400000 = 0000 0000 01 | 00 0000 0000 | 0000 0000 0000 so next data page will start from 0x00401000 = 0000 0000 01 | 00 0000 0001 | 0000 0000 0000 only one stack page: 0xFFFFF000 = 1111 1111 11 | 11 1111 1111 | 0000 0000 0000 Now, for second level page table, we will just require 1 Page which will contain following 3 distinct entries i.e. 0000 0000 00, 0000 0000 01, 1111 1111 11. Now, for each of these distinct entries, we will have 1-1 page in Level-1. Hence, we will have in total 4 pages and page size = 2^12 = 4KB. Therefore, Memory required to store page table = 4*4KB = 16KB.
Attention reader! Don’t stop learning now. Learn all GATE CS concepts with Free Live Classes on our youtube channel.