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GATE | GATE-CS-2003 | Question 11

  • Last Updated : 25 Nov, 2020

Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is
(A) Θ(1)
(B) Θ(log n)
(C) Θ(n)
(D) Θ(n2)

Answer: (C)

Explanation: Number of gates used in ‘n’ bit array multiplier (n * n) = (2n – 1)
Each gate in the circuit has a unit delay.

Total delay,

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= 1 * (2n – 1) 
= O(2n – 1) 
= O(n)  

Suppose 2 numbers A and B.


A = A0 A1 A2 A3
B = B0 B1 B2 B3 

For multiplying A and B we need to do,

  1. Multiply A0 A1 A2 A3 with B1 need 1 AND gate
  2. Multiply A0 A1 A2 A3 with B2 need 1 AND gate
  3. Multiply A0 A1 A2 A3 with B3 need 1 AND gate
  4. Multiply A0 A1 A2 A3 with B4 need 1 AND gate

Also 3 OR gates are required to add terms got by AND gates.
So, total gates required = 4+3 = 7 that is 2N-1.


Time complexity = ϴ(n) 

Option (C) is correct.

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