GATE | GATE-CS-2001 | Question 38

Consider the following data path of a simple non-pilelined CPU. The registers A, B, A1, A2, MDR, the bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8 × (2:1) and the DEMUX is of size 8 × (1:2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally.

GATECS2001Q40

The CPU instruction “push r”, where = A or B, has the specification

  M [SP]

How many CPU clock cycles are needed to execute the “push r” instruction?
(A) 1
(B) 3
(C) 4
(D) 5


Answer: (B)

Explanation: Push ‘r’ consist of following operations :

M[SP ]!R

SP!SP-1

‘r’ is stored at memory at address stack pointer currently is, this take 2 clock cycles

SP is then decremented to point to next top of stack

So total cycles=3

So (B) is correct option

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