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GATE | GATE CS 1999 | Question 61
  • Difficulty Level : Expert
  • Last Updated : 09 Oct, 2017

[5 Marks question]

An instruction pipeline consists of 4 stages: Fetch(F), Decode operand field (D), Execute (E), and Result-Write (W). The five instructions in a certain instruction sequence need these stages for the different number of clock cycles as shown by the table below.

No. of cycles needed for


Find the number of clock cycles needed to perform the 5 instructions.



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