Emitter Coupled Logic

ECL (emitter-coupled logic) is a high-speed integrated circuit bipolar transistor logic family in electronics. To avoid operating in the saturated (completely on) zone and its sluggish turn-off behavior, ECL employs an overdriven bipolar junction transistor (BJT) differential amplifier with a single-ended input and a restricted emitter current. ECL is also known as current-steering logic (CSL), current-mode logic (CML), or current-switch emitter-follower (CSEF) logic because the current is steered between two legs of an emitter-coupled pair.

Emitter-coupled logic (ECL) is the quickest of all logic families due to the accompanying reasons:

1. It is a non-saturated logic, as the transistors are not permitted to go into saturation. In this way, storage time delays are wiped out and, accordingly, the speed of operation is expanded.
2. Currents are kept high, and the result impedance is low to such an extent that circuit and stray capacitances can be immediately charged and released.
3. The restricted voltage swing.

The fact, ECL is still used in supercomputers and quick unique reasoning applications. Basic outputs are also available, the ECL gates may be connected ORed, and there are no noise spikes. Significant aspects of ECL gates are listed below:

1. Transistors will never reach saturation. With tpd = 1 ns, the speed is high.
2. The logic levels are negative, with logic 1 having a level of -0.9 V and logic 0 having a level of -1.7 V.
3. The noise margin is less, around 250 mV. This makes ECL untrustworthy for use in a weighty industrial climate. 
4. ECL circuits produce the result and supplement and kill the requirement for inverters.
5. Fan-out is enormous because the result impedance is low. It is around 25.
6. Power dissipation per entryway is enormous, PD = 40 mW.
7. The complete current flow in ECL is pretty much constant. So, no noise spikes will be internally created.

Features of Emitter-Coupled Logic’s (ECL)  

ECL family devices have numerous qualities that make them appealing for high-performance applications besides their high speed. The significant ones are as follows:

1. Devices of the ECL family operate without the need for any external inverters to simultaneously create the true and complementary output of the desired function at the outputs. Doing so reduces the number of packages, the amount of power needed, and the difficulties resulting from time delays that external inverters would otherwise create.
2. Achieving substantial fan-out and drive capabilities is made possible by the ECL gate structure’s inherent high input impedance and low output impedance.
3. Transmission line driving capability is provided by ECL devices with open emitter outputs. The outputs are impedance-matched to any line impedance. Furthermore, the absence of any pull-down resistors saves electricity.
4. Power supply design is made easier by the very consistent current drain that ECL devices provide.
5. ECL devices provide a broad range of performance flexibility due to the differential amplifier architecture, allowing ECL circuits to be employed as both linear and digital circuits.
6. Unused inputs can be easily terminated. Unused inputs can be left disconnected by using resistors of around 50k.
   

Working of ECL

ECL OR/NOR Gate: A two-input ECL OR/NOR gate is shown as:

ECL OR/NOR Gate:

ECL OR/NOR Gate features two complementary outputs. With transistors T2 and T1A, a differential amplifier is created. The transistors T1A and T1B are identical whereas with identical emitter and base voltages, transistors T3 and T4 are emitter followers (less than 0.8 V base to emitter drops). T1A and T1B receive inputs, and with a constant of 1.3 V, T2 is realizable.

When both inputs A and B are LOW, such as – 1.7 V. As a result of T2’s greater forward bias compared to T1A and T1B, T2 is active whereas T1A and T1B are not. R2’s value causes the collector to be at a voltage of roughly -0.9 V while the current through T2 is flowing. Due to this, the emitter of transistor T4 is at – 0.9 – 0.8 = – 1.7 V, indicating that the output of the OR is LOW. When passing through R1, the base current of T3 is incredibly little. The collectors of T1A and T1B are at approximately – 0.1 V because R1’s value is such that this current occurs. This causes the emitter of transistor T3 to be at – 0 1-0.8=-0.9 V, indicating that the NOR output is HIGH.

Since the relevant transistor is more forward-biased than T2 and is thus ON when A, B, or both A and B are HIGH, T2 is OFF when any one of these conditions exists. The consequence is that T1A and T1B’s collectors are at – 0.9 V, producing a NOR output, for instance, of – 0.9 – 0.8 = – 1.7 V, or logic 0. R2 only gets T4’s small base current as a result, T2’s collector is approximately at – 0.1 V, and logic 1’s OR output is – 0.1 – 0.8 = – 0.9 V. The OR/NOR gate in this circuit operates.

Common mode rejection, which reduces power supply noise that is shared by the two sides of the differential configuration, is one advantage of the differential input circuitry in ECL gates (difference out). The output impedance is also advantageously low since the ECL output is directed toward an emitter follower. The ECL gates as a result have a huge fan-out and are only a little impacted by capacitive loads. The emitter-follower output of some ECL gates has many outputs that come from various emitter transistors. One OR/NOR gate, for example, may have two OR outputs and two NOR outputs.

Wired OR Connection: With open-emitter outputs, or without resistors in the output emitter followers, the ECL gates are accessible. Simple connections between the open-emitter outputs are possible. A wired-OR operation may be performed by connecting the common emitter output terminal to a negative supply voltage (-5.2 V) using an external resistor.

Wired OR Connection

The transistors marked T3 are the output transistors of gate 1 and gate 2. At the point when the bases of both the transistors are at – 0.9 V, both the transistors conduct and make the common emitter voltage be, – 0.9 V – 0.8 V = – 13 V. At the point when both the bases are at – 0.1 V, again both the transistors conduct and make the output voltage to be, – 0.1 V – 0.8 V = – 0.9 V. At the point when just a single base is at – 0.1 V and the other at – 0.9 V, the output transistor with – 0.1 V base voltage conducts and makes the common emitter voltage – 0.9 V keeping the second transistor from conducting to provide the circuit OR operation.

B1	B2	Output
-0.9V	-0.9V	-1.7V
-0.9V	-0.1V	-0.9V
-0.1V	-0.9V	-0.9V
-0.1V	-0.1V	-0.9V

Characteristics of ECL:

The characteristics of ECL are as follows:

1. The enormous current need of the ECL family is one of its distinguishing features since it is essentially constant and barely varies with the state of the circuit.
2.  In contrast to other logic types, which need more current while switching than they do when quiescent, ECL circuits produce comparatively minimal power noise.
3. It has low noise immunity of about 0.2 – 0.25 V. 
4. ECL circuits are also less vulnerable to side-channel attacks such as differential power analysis in cryptography applications.
5. This configuration has a propagation time of less than 1 nanosecond or less, including the signal delay while switching on and off the IC package.
6. ECL has high power consumption, perhaps 60 Mw/gate.
7. ECL has always been the quickest logic family.

Advantages of ECL:

The advantages of ECL are as follows:

1. Among all logic families, ECL gates have the fastest speed since their BJTs work in the active region.
2. ECL has a significant benefit over CMOS switching in that its input stage’s current-steering behavior (Q1 and Q2) does not disrupt the system in the same way.
3. Although it costs more static electricity to attain this noise performance.
4. The outputs produced by ECL gates are complimentary (OR-NOR).
5. The wired-OR function can be implemented by coupling outputs.
6. There are no current switching spikes in power supply lines and the effects of temperature on parameters are minimal.
7. A single chip may perform a large number of functions and its standard supply voltage is -5.2 V.

Disadvantages of ECL:

The main disadvantages of ECL are as follows:

1. ECL gates are more expensive than TTL gates.
2. It has an extremely low noise margin (200 mV).
3. The highest power dissipation of any logic gates.
4. Its negative supply voltage and logic levels are not viable with other logic families (making it challenging to use ECL related to TTL and CMOS circuits).
5.  To interface with different logic families, level shifters are necessary.
6. The loading limitations of capacitors fan out.
7. VLSI design is complicated because ECL gates necessitate the fabrication of resistors.

Applications of ECL

The following are some of the emitter-coupled logic applications

1. Emitter-coupled logic is a logic and interfaces technology that is utilized in highly fast communications devices such as fiber-optic transceiver interfaces, Ethernet, and ATM (Asynchronous Transfer Mode) networks.
2. ECL is a logic family based on BJT that achieves high-speed operation by employing a very small voltage swing and avoiding transistor saturation.
3. ECL achieves an inverter function without needing stacked transistors by employing a single-ended bias i/p and positive feedback between primary & secondary transistors.
4. ECL is widely utilized in ultrafast or high-speed electronics.

Interfacing ECL Gates:

To connect ECL gates with other logic families, special level shifter circuits known as level translators are needed since ECL logic levels are not the same as those of TTL and CMOS circuits. To assist in the fusing of ECL with diverse families, level translators are available in several ECL series.