1. Multiple Cycle Datapaths: Multi-cycle datapaths break up instructions into separate steps. Each step takes a single clock cycle Each functional unit can be used more than once in an instruction, as long as it is used in different clock cycles. It reduces the amount of hardware needed. It reduces average instruction time. 2. Pipeline Datapaths: The goal of pipelining is to allow multiple instructions to be executed at the same time. We may need to perform several operations in a cycle. Increment the PC and add registers at the same time. Fetch one instruction while another one reads or writes data. Like the single-cycle datapath, a pipeline processor needs to duplicate hardware elements that are needed in the same clock cycle. Differences between Multiple Cycle Datapath and Pipeline Datapath :
| S.No. | Multiple Cycle Datapath | Pipeline Datapath |
|---|---|---|
| 1 | Instructions are divided into arbitrary number of steps. | Instructions are divided into one per stage. |
| 2 | Clock cycles are short but long enough for the lowest instruction. | Clock cycles are short but long enough for the lowest instruction. |
| 3 | There are only 1 instruction that can be executed at the same time. | There are as many instructions as pipeline stages. |
| 4 | There is a variable number of clock cycles per instructions. | There is a fixed number of clock cycles per instruction, one for each pipeline stage, i.e., CPI = k. |
| 5 | Control unit generates signals for the instruction’s current step and keeps track of the current step. | Control unit generates signals for the entire instruction; these signals are propagated from one pipeline stage to another via the pipeline registers. |
| 6 | There is no duplicate hardware, because the instructions generally are broken into single FU steps. | There is duplicate hardware, so that there are no restrictions on which instructions can be in the pipeline simultaneously. |
| 7 | Extra registers are required to hold the result of one step for use in the next step. | Extra registers are required to provide the results of one pipeline stage to the next pipeline stage. |
| 8 | Performance is slightly slower to moderately faster than single cycle, latter when the instructions steps are well balanced and a significantly fractions of the instructions take less than the maximum number of cycles. | Performance is moderately faster to significantly faster than a single cycle. |