Difference between Time Shared Bus, Crossbar Switch & Multiport Memory – Interconnection structure

Prerequisite : Detailed study about the Time Shared Bus, Crossbar Switch & Multiport Memory interconnection structure.

Introduction :
Interconnection structure can decide the overall system’s performance in a multi-processor environment. The processors must be able to share a set of main memory modules & I/O devices in a multiprocessor system. This sharing capability can be provided through interconnection structures. The interconnection structure that are commonly used can be given as follows :

1. Time shared / Common Bus (Discussed earlier)
2. Cross bar Switch
3. Multiport Memory
4. Multistage Switching Network (Discussed earlier)

5. Hypercube System

 Time shared / Common Bus :
In a multiprocessor system, the time shared bus interconnection provides a common communication path connecting all of the functional units. 

Time Shared/ Common bus in Multiprocessor System

Cross bar Switch :
A point is reached at which there is a separate path available for each memory module, if the number of buses in common bus system is increased. Crossbar Switch (for multiprocessors) provides a separate path for each module.

Cross-Bar Switch

Multiport Memory :
In Multiport Memory systems, the control, switching & priority arbitration logic are distributed throughout the crossbar switch matrix which is distributed at the interfaces to the memory modules.

Multiport Memory

Difference  between Time Shared Bus, Crossbar Switch & Multiport Memory :

	Time Shared Bus	Crossbar Switch	Multiport Memory
1.	Lowest cost for hardware & least complex.	Cost-effective for multiprocessors only as a basic switching matrix is required (to assemble functional units.)	As most of the control & switching circuitry is in the memory unit, it is expensive.
2.	System Expansion will degrade performance.	System Expansion can improve performance.	It is difficult to expand the system(design).
3.	Overall, system capacity limits the transfer rate & if the bus fails, the whole system will fail.	Transfer rate is high but more complex.	Potential for a very high total transfer rate.
4.	Modifying the hardware system configuration is easy.	Limited expansion of system, only by size of switch matrix.	Lots of cables & connectors are required.
5.	We cannot have transfers from all memory modules simultaneously.	We can have transfers from all memory modules simultaneously.	We can have transfers from all memory modules simultaneously.
6.	Lowest Efficiency & suitable for smaller systems only.	Functional Units are the simplest & cheapest.	Functional units permit low-cost-uniprocessor.