Data Hazards occur when an instruction depends on the result of previous instruction and that result of instruction has not yet been computed. whenever two different instructions use the same storage. location it must appear as if it is executed in sequential order.
There are four types of data dependencies: Read after Write (RAW), Write after Read (WAR), Write after Write (WAW), and Read after Read (RAR). These are explained as follows below.
- Read after Write (RAW) :
It is also known as True dependency or Flow dependency. It occurs when value produced by an instruction is required by a subsequent instruction. For example,
ADD R1, --, --; SUB --, R1, --;
Stalls are required to handle these hazards.
- Write after Read (WAR) :
It is also known as anti dependency. These hazards occur when the output register of an instruction is used for right after read by a previous instruction. For example,
ADD --, R1, --; SUB R1, --, --;
- Write after Write (WAR) :
It is also known as output dependency. These hazards occur when the output register of an instruction is used for write after written by previous instruction. For example,
ADD R1, --, --; SUB R1, --, --;
- Read after Read (RAR) :
It occurs when the instruction both read from the same register. For example,
ADD --, R1, --; SUB --, R1, --;
Since reading a register value does not change the register value, these Read after Read (RAR) hazards don’t cause a problem for the processor.
Handling Data Hazards :
These are various methods we use to handle hazards: Forwarding, Code recording, and Stall insertion.
These are explained as follows below.
- Forwarding :
It adds special circuitry to the pipeline. This method works because it takes for less time far the required values to travel through a wire than it does for a pipe line segment to compute its result.
- Code reordering :
We need a special type of software to reorder code. We call this type of software a hardware-dependent compiler.
- Stall Insertion :
it inserts one or more installs (no-op instructions) into the pipeline, which delays the execution of the current instruction until the required operand is written to the register file, but this method decreases pipeline efficiency and throughput.
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