Cray T3E Architecture
Cray T3E architecture are microprocessor for super-computing system. Cray T3E is a RISC(Reduced Instruction Set Computer) architecture which is very powerful microprocessors. T3E systems contain a large number of processing elements (PE). Each PE consists of a DEC Alpha EV5 RISC microprocessor.
Design features of Cray T3E architecture are as follows:
- The CRAY T3E is a scalable shared-memory multiprocessor
- The system architecture is designed to tolerate latency and enhance scalability.
- The T3E system was fully self-hosted and ran the UNICOS/mk distributed operating system.
- Cray T3E scalability can handle added processors and memory as well as larger I/O and interconnection bandwidths.
- Broad range implementation
- Cray T3E system has their own local memory.
Cray T3E Architecture:
T3E has its own local memory with capacity from 64 megabytes to 2 gigabytes. All address are represented using bytes. Two consecutive bytes form a word, four bytes form a longword, eight bytes form a quadword.
The Alpha architecture includes 32 general-purpose register from R0 to R31. R31 always contain the value zero. Each general-purpose register in Alpha architecture of Cray T3E system is 64-bit long. Other than 32 general-purpose register there are also 32 floating-point registers from F0 to F31 and F31 always contain zero value. Each floating-point register have 64-bit length.
- Data Formats:
- Integers are stored as longwords or quadwords.
- Characters are represented using 8-bit ASCII codes.
- Floating points are represented using two different floating-point formats.
- Instruction Formats:
In Cray T3E architecture there are basically five instruction formats. All of these formats are 32 bit long and first 6 bits of the instruction word represents the opcode. Some instruction formats also have an “functional” field in which function of different registers are specified.
- Addressing Modes:
Just like in most of the RISC architectures, the only instructions that deals with memory are load, store and branch instructions.
There are two modes to address operands in memory:
Mode Target address(TA) calculation PC-relative TA=(PC) + displacement Register indirect TA=(register) + displacement with displacement
Register indirect with displacement mode is used for load, store and subroutine jumps operations.
PC-relative mode is used for conditional and unconditional branches.
- Instruction Set:
Cray T3E architecture has approximately 130 machine instructions. Cray T3E architecture uses a large number of instructions to do the implementation of operations as fast as possible.
- Input and Output:
Cray T3E architecture uses multiple ports to perform I/O. These multiple ports have one or more I/O channels, which are integrated into the network that interconnects the processing nodes. All these channels are controllable and accessible from all PE’s (Processing Elements).
Attention reader! Don’t stop learning now. Get hold of all the important CS Theory concepts for SDE interviews with the CS Theory Course at a student-friendly price and become industry ready.