When we are using multiple general purpose registers, instead of single accumulator register, in the CPU Organization then this type of organization is known as General register based CPU Organization. In this type of organization, computer uses two or three address fields in their instruction format. Each address field may specify a general register or a memory word.If many CPU registers are available for heavily used variables and intermediate results, we can avoid memory references much of the time, thus vastly increasing program execution speed, and reducing program size.
MULT R1, R2, R3
This is an instruction of an arithmatic multiplication written in assembly language. It uses three address fields R1, R2 and R3. The meaning of this instruction is:
R1 <-- R2 * R3
This instruction also can be written using only two address fields as:
MULT R1, R2
In this instruction, the destination register is the same as one of the source registers. This means the operation
R1 <-- R1 * R2
The use of large number of registers results in short program with limited instructions.
Some examples of General register based CPU Organization are IBM 360 and PDP- 11.
The advantages of General register based CPU organization –
- Efficiency of CPU increases as there are large number of registers are used in this organization.
- Less memory space is used to store the program since the instructions are written in compact way.
The disadvantages of General register based CPU organization –
- Care should be taken to avoid unnecessary usage of registers. Thus, compilers need to be more intelligent in this aspect.
- Since large number of registers are used, thus extra cost is required in this organization.
General register CPU organisation of two type:
- Register-memory reference architecture (CPU with less register)– In this organisation Source 1 is always required in register, source 2 can be present either in register or in memory.Here two address instruction format is the compatible instruction format.
- Register-register reference architecture(CPU with more register)– In this organisation ALU operations are performed only on a register data. So operands are required in the register. After manipulation result is also placed in register.Here three address instruction format is the compatible instruction format.
- Cache Organization | Set 1 (Introduction)
- Cache Memory in Computer Organization
- Computer Arithmetic | Set - 1
- Computer Arithmetic | Set - 2
- Computer Organization and Architecture | Pipelining | Set 1 (Execution, Stages and Throughput)
- Computer Organization and Architecture | Pipelining | Set 3 (Types and Stalling)
- Computer Organization and Architecture | Pipelining | Set 2 (Dependencies and Data Hazard)
- Computer Organization | Amdahl's law and its proof
- Computer Organization | Hardwired v/s Micro-programmed Control Unit
- Computer Architecture | Flynn's taxonomy
- Clusters In Computer Organisation
- Generations of Computer
- Simplified Instructional Computer (SIC)
- Computer Organization | Micro-Operation
- Computer Organization | Different Instruction Cycles
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Improved By : VaibhavRai3