Bus Arbitration refers to the process by which the current bus master accesses and then leaves the control of the bus and passes it to the another bus requesting processor unit. The controller that has access to a bus at an instance is known as Bus master.
A conflict may arise if the number of DMA controllers or other controllers or processors try to access the common bus at the same time, but access can be given to only one of those. Only one processor or controller can be Bus master at the same point of time. To resolve these conflicts, Bus Arbitration procedure is implemented
to coordinate the activities of all devices requesting memory transfers. The selection of the bus master must take into account the needs of various devices by establishing a priority system for gaining access to the bus. The Bus Arbiter decides who would become current bus master.
There are two approaches to bus arbitration:
- Centralized bus arbitration – A single bus arbiter performs the required arbitration.
- Distributed bus arbitration – All devices participate in the selection of the next bus master.
Methods of BUS Arbitration –
There are three bus arbitration methods:
(i) Daisy Chaining method –
It is a centralized bus arbitration method. During any bus cycle, the bus master may be any device – the processor or any DMA controller unit, connected to the bus.
- Simplicity and Scalability.
- The user can add more devices anywhere along the chain, up to a certain maximum value.
- The value of priority assigned to a device is depends on the position of master bus.
- Propagation delay is arises in this method.
- If one device fails then entire system will stop working.
(ii) Polling or Rotating Priority method –
In this method, the devices are assigned unique priorities and complete to access the bus, but the priorities are dynamically changed to give every device an opportunity to access the bus.
- This method does not favor any particular device and processor.
- The method is also quite simple.
- If one device fails then entire system will not stop working.
- Adding bus masters is different as increases the number of address lines of the circuit.
(iii) Fixed priority or Independent Request method –
In this method, the bus control passes from one device to another only through the centralized bus arbiter.
- This method generates fast response.
- Hardware cost is high as large no. of control lines are required.
- Cache Organization | Set 1 (Introduction)
- Computer Organization | Cache Memory
- Computer Arithmetic | Set - 1
- Computer Arithmetic | Set - 2
- Computer Organization and Architecture | Pipelining | Set 1 (Execution, Stages and Throughput)
- Computer Organization and Architecture | Pipelining | Set 3 (Types and Stalling)
- Computer Organization and Architecture | Pipelining | Set 2 (Dependencies and Data Hazard)
- Computer Organization | Amdahl's law and its proof
- Computer Organization | Hardwired v/s Micro-programmed Control Unit
- Computer Architecture | Flynn's taxonomy
- Computer Organization | Multiplication Algorithm in Signed Magnitude Representation
- Clusters In Computer Organisation
- Generations of Computer
- Simplified Instructional Computer (SIC)
- Computer Organization | Micro-Operation
If you like GeeksforGeeks and would like to contribute, you can also write an article using contribute.geeksforgeeks.org or mail your article to firstname.lastname@example.org. See your article appearing on the GeeksforGeeks main page and help other Geeks.
Please Improve this article if you find anything incorrect by clicking on the "Improve Article" button below.