Computer Organization and Architecture | Pipelining | Set 3 (Types and Stalling)

Please see Set 1 for Execution, Stages and Performance (Throughput) and Set 2 for Dependencies and Data Hazard.   Types of pipeline

• Uniform delay pipeline In this type of pipeline, all the stages will take same time to complete an operation. In uniform delay pipeline, Cycle Time (Tp) = Stage Delay If buffers are included between the stages then, Cycle Time (Tp) = Stage Delay + Buffer Delay
• Non-Uniform delay pipeline In this type of pipeline, different stages take different time to complete an operation. In this type of pipeline, Cycle Time (Tp) = Maximum(Stage Delay) For example, if there are 4 stages with delays, 1 ns, 2 ns, 3 ns, and 4 ns, then Tp = Maximum(1 ns, 2 ns, 3 ns, 4 ns) = 4 ns If buffers are included between the stages, Tp = Maximum(Stage delay + Buffer delay) Example : Consider a 4 segment pipeline with stage delays (2 ns, 8 ns, 3 ns, 10 ns). Find the time taken to execute 100 tasks in the above pipeline. Solution : As the above pipeline is a non-linear pipeline, Tp = max(2, 8, 3, 10) = 10 ns We know that ET_pipeline = (k + n – 1) Tp = (4 + 100 – 1) 10 ns = 1030 ns NOTE: MIPS = Million instructions per second

Performance of pipeline with stalls

Speed Up (S) = Performancepipeline / Performancenon-pipeline
=> S = Average Execution Timenon-pipeline / Average Execution Timepipeline
=> S = CPInon-pipeline * Cycle Timenon-pipeline / CPIpipeline * Cycle Timepipeline
=> S = CPInon-pipeline * Clock frequency pipeline / CPIpipeline * Clock frequencynon-pipeline

Ideal CPI of the pipelined processor is ‘1’. But due to stalls, it becomes greater than ‘1’. =>

S = CPInon-pipeline * Cycle Timenon-pipeline  / (1 + Number of stalls per Instruction) * Cycle Timepipeline

As Cycle Timenon-pipeline =   Cycle Timepipeline,

Speed Up (S) = CPInon-pipeline / (1 + Number of stalls per instruction) 

Problems  in Instruction Pipelining

• Time Variation:Not all stages take the same amount of time.This means that the speed gain of a pipeline will be determined by its slowest page. This problem is particularly acute in instruction processing, since different instructions have different operand requirements and sometimes vastly different processing time.
• Data Hazards: When several instructions are in parallel execution, a problem arises if they referenece the same data. We must ensure that a later instruction  does not attempt to access data source than a proceeding instruction, If they will lead to incorrect results.
• Branching: In order to fetch the “next” instruction may not Know which one is required. If the present instruction is a conditional branch, the next instruction may not be known until the current one is processed.
• Interrupts: Interrupts insert unplanned ” extra” instructions into the instruction stream. The interrupt must take effect between instructions, that is when one instruction has completed and the next has not yet began.

Sources : goo.gl/J9KVNt https://en.wikipedia.org/wiki/Hazard_(computer_architecture) https://en.wikipedia.org/wiki/Data_dependency   This article has been contributed by Saurabh Sharma.   Please write comments if you find anything incorrect, or you want to share more information about the topic discussed abovePro

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