Computer Organization and Architecture | Pipelining | Set 3 (Types and Stalling)

Please see Set 1 for Execution, Stages and Performance (Throughput) and Set 2 for Dependencies and Data Hazard.

Types of pipeline

• Uniform delay pipeline
  In this type of pipeline, all the stages will take same time to complete an operation.
  In uniform delay pipeline, Cycle Time (Tp) = Stage Delay

  If buffers are included between the stages then, Cycle Time (Tp) = Stage Delay + Buffer Delay

• Non-Uniform delay pipeline
  In this type of pipeline, different stages take different time to complete an operation.
  In this type of pipeline, Cycle Time (Tp) = Maximum(Stage Delay)

  For example, if there are 4 stages with delays, 1 ns, 2 ns, 3 ns, and 4 ns, then

  Tp = Maximum(1 ns, 2 ns, 3 ns, 4 ns) = 4 ns

  If buffers are included between the stages,

  Tp = Maximum(Stage delay + Buffer delay)

  Example : Consider a 4 segment pipeline with stage delays (2 ns, 8 ns, 3 ns, 10 ns). Find the time taken to execute 100 tasks in the above pipeline.
  Solution : As the above pipeline is a non-linear pipeline,
  Tp = max(2, 8, 3, 10) = 10 ns
  We know that ET_pipeline = (k + n – 1) Tp = (4 + 100 – 1) 10 ns = 1030 ns

  NOTE: MIPS = Million instructions per second

Performance of pipeline with stalls

Speed Up (S) = Performancepipeline / Performancenon-pipeline
=> S = Average Execution Timenon-pipeline / Average Execution Timepipeline
=> S = CPInon-pipeline * Cycle Timenon-pipeline / CPIpipeline * Cycle Timepipeline

Ideal CPI of the pipelined processor is ‘1’. But due to stalls, it becomes greater than ‘1’.
=>

S = CPInon-pipeline * Cycle Timenon-pipeline  / (1 + Number of stalls per Instruction) * Cycle Timepipeline

As Cycle Timenon-pipeline =   Cycle Timepipeline,

Speed Up (S) = CPInon-pipeline / (1 + Number of stalls per instruction) 

Sources : goo.gl/J9KVNt
https://en.wikipedia.org/wiki/Hazard_(computer_architecture)
https://en.wikipedia.org/wiki/Data_dependency

This article has been contributed by Saurabh Sharma.

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