# Combinational Circuits

• Last Updated : 19 Nov, 2018

 Question 1
In the following truth table, V = 1 if and only if the input is valid. What function does the truth table represent? Priority encoder Decoder Multiplexer Demultiplexer

Question 1-Explanation:
Since there are more than one outputs and number of outputs is less than inputs, it is a Priority encoder V=1 when input is valid and for priority encoder it checks first high bit encountered. Except all are having at least one bit high and ‘x’ represents the “don’t care” as we have found a high bit already. So answer is (A).
 Question 2
What is the Boolean expression for the output f of the combinational logic circuit of NOR gates given below?  (Q+R)' (P+Q)' (P+R) (P+Q+R)'

Question 2-Explanation:
Answer is Option A. The above question contains the NOR gates. Let's see what NOR gate does. If A and B are the two inputs to the NOR gate, the NOR gate gives (A+B)' as the output. Let's assign numbers to the Gates for the easy understanding.
```In the 1st column there are 4 NOR Gates,
number them as 1 to 4 ( top to down).

In the 2nd column there are 2 NOR Gates,
number them as 5 and 6 ( top to down).

In the 3rd column there is only 1 NOR Gate,
number it as 7.

1st numbered Gate gives output as : ( P + Q )'
2nd numbered Gate gives output as : ( Q + R )'
3rd numbered Gate gives output as : ( P + R )'
4th numbered Gate gives output as : ( R + Q )'
5th numbered Gate gives output as :
(( P + Q )' + ( Q + R )')'
= ((P + Q)'' . ( Q + R )'') ( De Morgan's law)
= (P + Q ) . ( Q + R ) ( Idempotent Law, A'' = A)
= (PQ + PR + Q + QR )
= (Q(1 + P + R) + PR) = Q + PR ( as, 1 + " any
boolean expression" = 1 )

Similarly 6th numbered Gate gives output as : R + PQ
(as this time R is common here)

Now 7th numbered Gate gives output as :
((Q + PR) + (R + PQ))'
= (Q( 1+P) + R(1+P))'
= (Q+R)' ```
 Question 3
How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates? 7 8 9 10

Question 3-Explanation: So total signals in=a, b, c, x, y, z  i.e. 6 And total output =8*8=64 hence required decoders (from fig.) = 9  so ans is ( C) part.
 Question 4
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed? 2n line to 1 line 2n+1 line to 1 line 2n-1 line to 1 line 2n-2 line to 1 line

Question 4-Explanation:
We can use n-1 selection lines , and using 0,1 and nth variable and its compliment to realize the function So ans is 2^(n-1):1  Part-(C )
 Question 5
In a look-ahead carry generator, the carry generate function Gi and the carry propagate function Pi for inputs Ai and Bi are given by:
`Pi = Ai ⨁ Bi and Gi = AiBi `
The expressions for the sum bit Si and the carry bit Ci+1 of the look-ahead carry adder are given by:
`Si = Pi ⨁ Ci and Ci+1 = Gi + PiCi , where C0 is the input carry. `
Consider a two-level logic implementation of the look-ahead carry generator. Assume that all Pi and Gi are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator for a 4-bit adder with S3, S2, S1, S0 and C4 as its outputs are respectively: 6, 3 10, 4 6, 4 10, 5

Question 5-Explanation:
let the carry input be c0 Now,
```c1 = g0 + p0c0 = 1 AND, 1 OR
c2 = g1 + p1g0 + p1p0c0
= 2 AND, 1 OR

c3 = g2 + p2g1 + p2p1go + p2p1p0c0
= 3 AND, 1 OR
c4 = g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0
= 4 AND, 1 OR```
So, total AND gates = 1+2+3+4 = 10 , OR gates = 1+1+1+1 = 4 So as a general formula we can observe that we need a total of " n(n+1)/2 " AND gates and "n" OR gates for a n-bit carry look ahead circuit used for addition of two binary numbers.
 Question 6
Consider a 4-to-1 multiplexer with two select lines S1 and S0, given below The minimal sum-of-products form of the Boolean expression for the output F of the multiplexer is P'Q + QR' + PQ'R P'Q + P'QR' + PQR' + PQ'R P'QR + P'QR' + QR' + PQ'R PQR'

Question 6-Explanation:
For 4 to 1 mux =p’q’(0)+p’q(1)+pq’r+pqr’ =p’q+pq’r+pqr’ =q(p’+pr’)+pq’r =q(p’+r’)+pq’r =p’q+qr’+pq’r Ans (a)
 Question 7
Consider the following combinational function block involving four Boolean variables x, y, a, b where x, a, b are inputs and y is the output.
```f (x, y, a, b)
{
if (x is 1) y = a;
else y = b;
}
```
Which one of the following digital logic blocks is the most suitable for implementing this function? Full adder Priority encoder Multiplexer Flip-flop

Question 7-Explanation:
This function can be interpreted as having two inputs a, b and select signal x. Output y will depend on the select signal x. Function will be like (ax+bx’) Its implementation will be like So ans is ( C) part.
 Question 8 Consider the circuit above. Which one of the following options correctly represents f (x, y, z)? xz' + xy + y'z xz' + xy + (yz)' xz + xy + (yz)' xz + xy' + y'z

Question 8-Explanation:
Output from MUX 1=> Z’X+ZY’ Output from MUX2=> Y’(Z’X+ZY’)+YX =>Y’Z+Y’Z’X+YX =>Y’Z+X(Y’Z’+Y) =>Y’Z+X(Y+Z’)        USING A+A’B=(A+B) =>Y’Z+XY+XZ’ So Ans is (A).
 Question 9
Given two three bit numbers a2a1a0 and b2b1b0 and c, the carry in, the function that represents the carry generate function when these two numbers are added is:  A B C D

Question 9-Explanation:
For carry look ahead adder we know carry generate function--- Where   As we are having two 3 bits number to add so final carry out will be C3- Putting value of Pi,Gi in 3 C3=(A2.B2)+(A1.B1)(A2+B2)+(A0.B0)(A1+B1)(A2+B2)                       (TAKING C0=0) C3=A2.B2 +A1A2B1+A1B2B1+(A0B0)(A1A2+A1B2+B1A2+B1B2) C3=A2B2+A1A2B1+A1B2B1+A0A1A2B0+A0A1B0B2+A0A2B1B0+A0B0B1B2 SO ANS IS (A) PART.
 Question 10
We consider the addition of two 2’s complement numbers bn-1bn-2...b0 and an-1an-2...a0. A binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by cn-1cn-2...c0 and the carry-out by cout. Which one of the following options correctly identifies the overflow condition?  A B C D

Question 10-Explanation:
Overflow occurs only when two same sign binary numbers added and result of these numbers is different sign in 2's complement representation. Otherwise overflow can not be occurred. Counter example for given options (A) 0111+0111=1110 has overflow, but given condition violates. (C) 1001+0001=1010 has no overflow, but given condition violates. (D) 1111+1111=1110 has no overflow, but given condition violates. Only option (B) is correct.
There are 55 questions to complete.