Cache and main memory

Question 1

Consider a set-associative cache of size 2KB (1KB=2¹⁰ bytes) with cache block size of 64 bytes. Assume that the cache is byte-addressable and a 32 -bit address is used for accessing the cache. If the width of the tag field is 22 bits, the associativity of the cache is _________ .

• 2
• 4
• 1
• 8

Question 2

Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular intervals. Consider a 2 MHz processor. If 0.5% processor cycles are used for DMA, the data transfer rate of the device is __________ bits per second.

• 80000
• 10000
• 8000
• 1000

Question 3

Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements.

• S1: Read misses in a write through L1 cache do not result in writebacks of dirty lines to the L2
• S2: Write allocate policy must be used in conjunction with write through caches and no-write allocate policy is used with writeback caches.

Which of the following statements is correct?

• S1 is true and S2 is false
• S1 is false and S2 is true
• S1 is true and S2 is true
• S1 is false and S2 is false

Question 4

In a k-way set associative cache, the cache is divided into v sets, each of which consists of k lines. The lines of a set are placed in sequence one after another. The lines in set s are sequenced before the lines in set (s+1). The main memory blocks are numbered 0 onwards. The main memory block numbered j must be mapped to any one of the cache lines from.

• (j mod v) * k to (j mod v) * k + (k-1)
• (j mod v) to (j mod v) + (k-1)
• (j mod k) to (j mod k) + (v-1)
• (j mod k) * v to (j mod k) * v + (v-1)

Question 5

A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 × 4 decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is

• 4
• 5
• 6
• 7

Question 6

A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The number of bits in the tag field of an address is

• 11
• 14
• 16
• 27

Question 7

Consider the data given in previous question. The size of the cache tag directory is

• 160 Kbits

• 136 bits

• 40 Kbits

• 32 bits

Question 8

An 8KB direct-mapped write-back cache is organized as multiple blocks, each of size 32-bytes. The processor generates 32-bit addresses. The cache controller maintains the tag information for each cache block comprising of the following. 1 Valid bit 1 Modified bit As many bits as the minimum needed to identify the memory block mapped in the cache. What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache?

• 4864 bits
• 6144 bits
• 6656 bits
• 5376 bits

Question 9

A main memory unit with a capacity of 4 megabytes is built using 1M × 1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is:- 
A.100 nanoseconds
B.100×2¹⁰ nanoseconds
C.100×2²⁰ nanoseconds
D.3200×2²⁰ nanoseconds

• A

• B

• C

• D

Question 10

A computer system has an L1 cache, an L2 cache, and a main memory unit connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds. 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory unit respectively. When there is a miss in L1 cache and a hit in L2 cache, a block is transferred from L2 cache to L1 cache. What is the time taken for this transfer?

• 2 nanoseconds
• 20 nanoseconds
• 22 nanoseconds
• 88 nanoseconds