Bus Cycles of 8086 Microprocessor

The bus cycle is also named as machine cycle. Bus cycle of 8086 is used to access memory, peripheral devices (Input/Output devices), and Interrupt controller. Bus cycle corresponds to a sequence of events that starts with an address being output on system address bus followed by a write or read data transfer. During these operations, a series of control signals are also produced by microprocessor to control direction and timing of bus.

There are at least four clock periods in a bus cycle of 8086 microprocessor. These four clock periods are called T₁, T₂, T₃ and T₄ states.

These four clock states gives bus cycle duration T of 200 ns *4 = 800 ns in 5-MHz 8086 system.

1. Read Cycle :
   When a read cycle is to be performed, during T₁ microprocessor puts an address on address bus, and then bus is put in high impedance state during T₂ state. Data to be read must be out on bus during T₃ and T₄. During T₃ bus is made “reserved for data in” and finally data is read during T₄.

   

2. Write Cycle :
   In case of write memory cycle, during T₁ state microprocessor puts an address on address bus. Data is put on data bus by CPU during T₂ state and maintained during T₃ and T₄ states, that is written out to memory or I/O devices.