Block Diagram of 8259 Microprocessor
- 8259 microprocessor can be programmed according to given interrupts condition and it can be provided either with level or edge triggered interrupt level.
- It can be programmed either work in 8085 or in 8086 microprocessors.
- Individual interrupt bits can be masked.
- By conducting more number of 8259 we can get upto 64 interrupt pins.
It contains 3 rigisters commonly known as ISR, IRR, IMR & there is 1 priority resolver (PR).
Attention reader! Don’t stop learning now. Get hold of all the important CS Theory concepts for SDE interviews with the CS Theory Course at a student-friendly price and become industry ready.
- Interrupt Request Register (IRR): It stores those bits which are requesting for their interrupt services.
- Interrupt Service Register (ISR): It stores that interrupt levels which is currently being servied.
- Interrupt Mask Register (IMR): It stores that interrupt levels which have to be masked. These interrupts levels are already acccepted by 8259 microprocessor.
Priority Resolver (PR): It examines all the 3 registers and set the priority of interrupts and set the interrupt levels in ISR which has highest priority and rest the interrupt bit is IRR which is already accepted.
SP/EN (low active pin): If its value is 1 it works in master mode & if its value=e is 0 then it works in slave mode.
Cascade Buffer: It is used to cascade more number of Programmable Interrupt Controller to increase the interrupts handling capability upto 64 level.