Block Diagram of 8259 Microprocessor
- 8259 microprocessor can be programmed according to given interrupts condition and it can be provided either with level or edge-triggered interrupt level.
- It can be programmed to either work in 8085 or in 8086 microprocessors.
- Individual interrupt bits can be masked.
- By conducting more number of 8259 we can get up to 64 interrupt pins.
It contains 3 registers commonly known as ISR, IRR, IMR & there is 1 priority resolver (PR).
- Interrupt Request Register (IRR): It stores those bits which are requested for their interrupt services.
- Interrupt Service Register (ISR): It stores the interrupt levels which is currently being served.
- Interrupt Mask Register (IMR): It stores interrupt levels that have to be masked. These interrupt levels are already accepted by the 8259 microprocessor.
Priority Resolver (PR): It examines all the 3 registers and sets the priority of interrupts and sets the interrupt levels in ISR which has the highest priority and the rest of the interrupt bit is IRR which is already accepted.
SP/EN (low active pin): If its value is 1 it works in master mode & if its value=e is 0 then it works in slave mode.
Cascade Buffer: It is used to cascade more number of Programmable Interrupt Controller to increase the interrupts handling capability up to 64 levels.
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