1. Arithmetic Pipeline :
An arithmetic pipeline divides an arithmetic problem into various sub problems for execution in various pipeline segments. It is used for floating point operations, multiplication and various other computations. The process or flowchart arithmetic pipeline for floating point addition is shown in the diagram.
Floating point addition using arithmetic pipeline :
The following sub operations are performed in this case:
- Compare the exponents.
- Align the mantissas.
- Add or subtract the mantissas.
- Normalise the result
First of all the two exponents are compared and the larger of two exponents is chosen as the result exponent. The difference in the exponents then decides how many times we must shift the smaller exponent to the right. Then after shifting of exponent, both the mantissas get aligned. Finally the addition of both numbers take place followed by normalisation of the result in the last segment.
Let us consider two numbers,
X=0.3214*10^3 and Y=0.4500*10^2
First of all the two exponents are subtracted to give 3-2=1. Thus 3 becomes the exponent of result and the smaller exponent is shifted 1 times to the right to give
Finally the two numbers are added to produce
As the result is already normalized the result remains the same.
2. Instruction Pipeline :
In this a stream of instructions can be executed by overlapping fetch, decode and execute phases of an instruction cycle. This type of technique is used to increase the throughput of the computer system. An instruction pipeline reads instruction from the memory while previous instructions are being executed in other segments of the pipeline. Thus we can execute multiple instructions simultaneously. The pipeline will be more efficient if the instruction cycle is divided into segments of equal duration.
In the most general case computer needs to process each instruction in following sequence of steps:
- Fetch the instruction from memory (FI)
- Decode the instruction (DA)
- Calculate the effective address
- Fetch the operands from memory (FO)
- Execute the instruction (EX)
- Store the result in the proper place
The flowchart for instruction pipeline is shown below.
Let us see an example of instruction pipeline.
Here the instruction is fetched on first clock cycle in segment 1.
Now it is decoded in next clock cycle, then operands are fetched and finally the instruction is executed. We can see that here the fetch and decode phase overlap due to pipelining. By the time the first instruction is being decoded, next instruction is fetched by the pipeline.
In case of third instruction we see that it is a branched instruction. Here when it is being decoded 4th instruction is fetched simultaneously. But as it is a branched instruction it may point to some other instruction when it is decoded. Thus fourth instruction is kept on hold until the branched instruction is executed. When it gets executed then the fourth instruction is copied back and the other phases continue as usual.
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- Difference between Linear Pipeline and Non-Linear Pipeline
- Various Instructions for five stage Pipeline
- Differences between Multiple Cycle Datapath and Pipeline Datapath
- Computer Organization | Instruction Formats (Zero, One, Two and Three Address Instruction)
- Difference between 3-address instruction and 0-address instruction
- Difference between 3-address instruction and 1-address instruction
- Instruction Set used in SIC/XE
- Vector instruction types
- Timing diagram of MVI instruction
- Microarchitecture and Instruction Set Architecture
- Instruction Set used in simplified instructional Computer (SIC)
- Instruction cycle in 8085 microprocessor
- Instruction Word Size in Microprocessor
- Essential Registers for Instruction Execution
- Timing diagram of MOV Instruction in Microprocessor
- Computer Organization | Different Instruction Cycles
- Computer Organization | Problem Solving on Instruction Format
- 8086 program to transfer a block of bytes by using string instruction
- Difference between 2-address instruction and 1-address instructions
- Vector Instruction Format in Vector Processors
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