Aptitude | GATE IT 2006 | Question 8

Which of the following DMA transfer modes and interrupt handling mechanisms will enable the highest I/O band-width?  

(A)

Transparent DMA and Polling interrupts

(B)

Cycle-stealing and Vectored interrupts

(C)

Block transfer and Vectored interrupts

(D)

Block transfer and Polling interrupts

Answer: (C)

Explanation:

Among the options provided, the DMA transfer mode and interrupt handling mechanism that enable the highest I/O bandwidth is option (C): Block transfer and Vectored interrupts.

Let’s understand why this choice provides the highest I/O bandwidth:

1. Transparent DMA: Transparent DMA is not the most efficient option for achieving high I/O bandwidth. It allows the DMA controller to directly access the memory and transfer data without CPU involvement. However, it doesn’t utilize interrupts effectively for signaling completion or handling data transfer events.
2. Cycle-stealing: Cycle-stealing DMA interrupts the CPU during its normal operation to transfer data. While it can improve I/O bandwidth, it interrupts the CPU frequently, affecting its performance.
3. Block transfer: Block transfer DMA involves transferring a block of data in a single operation. It minimizes the number of interrupts needed for transferring large amounts of data, resulting in efficient data transfer.
4. Polling interrupts: Polling interrupts require the CPU to check the status of the DMA controller repeatedly to determine if data transfer has completed. This approach involves continuous CPU involvement and wastes CPU cycles, making it less efficient for achieving high I/O bandwidth.
5. Vectored interrupts: Vectored interrupts allow the DMA controller to directly inform the CPU about data transfer events, reducing the CPU overhead. The CPU can efficiently handle the interrupts and resume its normal operations.

Considering the characteristics described above, option (C) combines block transfer DMA, which minimizes interrupts for large data transfers, with vectored interrupts, which efficiently notify the CPU about data transfer events. This combination maximizes the I/O bandwidth by reducing CPU involvement and efficiently utilizing interrupts, making it the best choice among the provided options for achieving the highest I/O bandwidth.

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