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68000 Family Registers and Addressing In Computer Architecture
  • Difficulty Level : Medium
  • Last Updated : 23 Feb, 2021

The 68000 processor is characterized by a 16-bit external word length as the processor chip has 16 data pins for connection to the memory. However, data are manipulated inside the processor in registers that contain the 32 bits. Other models for this family are 68020, 68030, and 68040 processors., which come in both large chip packages and have 32-bit external data pins. Thus, they can deal with data both internally and externally in 32-bit quantities. 

The 68000 Register Structure :
The 68000 register structure, has 8 data registers and 8 address registers, each 32 bit long. The data registers serve as general-purpose accumulators as counters. Following is the structure for the same is given below.

 

The 68000 instructions deal with operands of three different lengths. A 32-bit operand is said to be occupied long word, a 16-bit operand constitutes a word, and an 8-bit operand is a byte. When an instruction uses a byte or a word operand in a register, the operand is in the low-order bit positions of the register. In most cases, such instructions do not affect the remaining high-order bits of the register, but some instructions extend the sign of a shorter operand into the high-order bits.



The address registers hold the information used in the determination of the addresses of memory operands. This information may be given in either long word or word sizes. When the address of a given memory location is an address register serves as a pointer to that location. Both address and data registers can also be used as index registers. One address register, A7, has the special function of being the processor stack pointer. The address registers and address calculations involve 32 bits. However, in the case of 68000, only the least significant 24 bits of an address are used externally to access the memory. The 68020, 68030, 68040 processors have 32 external address lines as well as 32 data lines.

Addressing : 

  • The memory of a 68000 computer is organized in 16-bit words and is byte-addressable. Two consecutive words can be interpreted as a single 32-bit long word. Memory addresses are assigned as shown in the above diagram. A word must be aligned on an even boundary (that is its address must be an even number). The big-endian address assignment is used. The byte in the high-order position of a word has the same address as the word, whereas the byte in the low-order position has the next higher address. 
     
  • Since the 68000 generates 24-bit addresses, its addressable space is 224 (16,777,216 or 16M) bytes. This addressable space may be thought of as consisting of 512 (29) pages of 32K (215) bytes each. Thus, hexadecimal addresses 0 to 7FFF constitute page 0, addresses 8000 to FFFF makeup page 2, and so on. The last page consists of addresses of FF8000 to FFFFFF.
     
  • The 68000 has several addressing modes. Many of the 68000’s instructions fit into a 16-bit word, but some require additional words for extra addressing information. The first word of instruction is the OP-code word, which specifies the operation to be performed and gives some addressing information. The rest of the information is given in subsequent words.

Different types of Modes in Addressing :
Following are the different addressing modes available as follows.

  1. Immediate Mode 
  2. Absolute Mode 
  3. Register Mode 
  4. Register Indirect Mode 
  5. Auto-increment Mode 
  6. Auto decrement Mode 
  7. Basic Index mode 
  8. Full Index Mode 
  9. Basic Relative Address 
  10. Full Relative Mode 

Syntax and function of Addressing modes :
Let’s have a look at the evaluation part of the addressing modes as follows.

Name

Assebler Syntax

Addressing Function



Immediate

#Value

Operand = Value

Absolute Short

Value

EA = Sign Extended WValue

Absolute Long

Value

EA = Value

Register

Rn

EA = Rn

Operand = [Rn]

Regsiter Indirect

(An)

EA = [An];

Autoincrement

(An)+

EA = [An]

Increment An

Autodecrement

-(An)

Decrement An

EA = [An]

Indexed Basic

WValue(An)

EA = WValue + [An]

Indexed Full

BValue(An,Rk,S)

EA = BValue + [An] + [Rk]

Relative Basic

WValue(PC) or Label

EA = WValue + [PC]

Relative Full

BValue(PC,Rk,S) or Label (Rk)

EA =BValue + [PC] + [Rk]

Here, you will see the meaning of terms.

EA       = effective address
Value    = a number given either explicitly or represented by a label
BValue   = an 8-bit value 
WValue   = an 16-bit value
An       = an address register
Rk       = an address or a data register
S       = a size indicator: W for sign-extended 16-bit word and L stands for 32-bit long word

Example –
Let’s do a quick example to understand it. Consider the instruction ADD 100(PC,A1),D0. When encoded in machine form, this instruction consists of 2 words. The OP-code word specifies that this is an ADD instruction, that the destination register is data register D0 and the full relative addressing mode is used for the source operand. The second word, also called extension word, specifies that register A1 is used as the index register, and it contains the offset value 100 enclosed in 8 bits.

Assume that the preceding instruction is stored in a location 1000 and register A1 contains the value 6. When the OP-code word of this instruction has been fetched and while it is being decoded by the processor, the program counterpoints to the extension word, which means that the program counter contains the value 1002. Therefore, the effective address of the source operand is as follows.

EA = [PC] + [A1] + 100 = 1002 + 6 +100 = 1108

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