Which of the following statement(s) is/are not correct?

• I. If associativity of a processor cache is doubled while keeping the capacity and block size unchanged, it will not affect the width of processor to main memory bus.
• II. Misses occur due to the contention of multiple blocks for the same cache set are compulsory misses.
• III. Misses occur due to first time access to the block are conflict misses.

(A) Only I and II
(B) Only I and III
(C) Only II and III
(D) All I, II and III


Answer: (C)

Explanation: Only statement (I) is correct.

• Misses occur due to the contention of multiple blocks for the same cache set are conflict misses.
• Misses occur due to first time access to the block are compulsory misses.

So, option (C) is true.

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