Consider the following Shift register which is initially loaded with 00101 followed by a clock after each clock pulse pattern get shifted towards the right by one bit and with each shift serial input is pushed to the LSB then after how many clock cycles shift register data will be same again?

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(A) 5
(B) 7
(C) 9
(D) 12


Answer: (D)

Explanation: Since first circuit is indirect the implementation of Exclusive-or gate and second gate is Exclusive-or.

Therefore, output of previous operation, which will became input to the next operation:

Input: 00101
1:  00010 
2:  00001
3:  10000
4:  01000
5:  10100
6:  11010
7:  11101
8:  11110
9:  01111
10: 10111
11: 01011
12: 00101, which is same as initial input. 

So, option (D) is correct.

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  • Last Updated : 28 Nov, 2018

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