Consider the following statements regarding implementations of half-adder and half-subtractor:

1. Total 5 NAND gates are required to implement half adder and 5 NAND gates are required to implement half subtractor.
2. Total 5 NAND gates are required to implement half adder and 5 NOR gates are required to implement half subtractor.
3. Total 5 NOR gates are required to implement half adder and 5 NAND gates are required to implement half subtractor.
4. Total 5 NOR gates are required to implement half adder and 5 NOR gates are required to implement half subtractor.

(A) Only 1, 2 and 3 are correct
(B) Only 2 and 3 are correct
(C) Only 1 and 4 are correct
(D) All 1, 2, 3, and 4 are correct


Answer: (D)

Explanation: Total 5 NAND (or 5 NOR) gates are required to implement half adder and 5 NAND (or 5 NOR) gates are required to implement half subtractor.

Option (D) is correct.

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