Consider the following instruction set:

1. Add: r0 r1 r2
2. Sub: r3 r0 r4
3. Mul: r4 r5 r6 
4. Div: r3 r7 r8 

In order execution creates unnecessary stalls, to avoid these stalls instruction rescheduling takes place, e.g., 1 – 3 – 4 – 2 but it creates ______ dependency between 3 and 2 and ______ dependency between 2 and 4.

(A) Data dependency and anti-dependency respectively
(B) Anti-data dependency and output dependency respectively
(C) Output dependency and anti -data dependency respectively
(D) Anti-data dependency and data dependency respectively


Answer: (B)

Explanation: When instruction 1 – 2 -3 – 4 executed then 2nd instruction is dependent on 1st for r0 and will create stalls. These stalls are also shared by 3rd and 4th instruction even they are independent. To handle this insert independent instruction in place of the stall. So it will cause the reorder execution 1 – 3 – 4 – 2.

Instruction 3 modifies the data register r4 before 2 reads it, therefore, instruction 2 gets the new value[data loss]. This is called Anti data dependency, also known as write-after-read (WAR).

Instruction 4 will modify the register r3 before instruction 2 write it, therefore, destination is incorrectly updated with a hold value[data loss] is called output dependency, also known as write-after-write (WAW).

So, option (B) is correct.


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  • Last Updated : 22 Nov, 2018

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