A computer system which supports 16 way set associative cache of 256 MB with a block size of 8 bytes. CPU support 32-bit address to access the data. Each tag contains 1 valid bit and 1 replacement bit. How much space is required in the cache controller to store the tag information?
(A) 30 MB
(B) 40 MB
(C) 50 MB
(D) None of these


Answer: (B)

Explanation: According to given data, instruction size is 32 bits.
Word size is 8 byte (= 2³), so word offset (W.O.) is 3 bits
Cache size 256 MB (= 2²⁸), so line offset is (28 – 3) = 25 bits
And for given 16 (= 2⁴) sets cache, set offset (S.O.) = 25 – 4 = 21 bits

Now, remaining bits are used for tag = 32 – (21 + 3) = 8 bits.

Therefore, tag memory size

= S * P * tag bits
= 221 * 16 * (8 + 1 valid bit + 1 replacement)
= 10 * 225 
= 320 M bits
= 40 MB  

So, option (B) is correct.

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